• 专利附录
  • 专利说明
  • 权利要求
  • 类似技术
  • 同族专利
  • 引用文献
  • 法律状态
  • 优先权
    • 专利摘要:
    A semiconductor device corresponding to a jfet type transistor having a multi-layer arrangement of several materials is detailed, giving as a result of that arrangement a vertical jfet type transistor device; that is, the current flows from the top of the chip (source) to the bottom (drain), through the entire silicon block, while in a second aspect of the invention there is a method for manufacturing the jfet device of the first aspect; method that makes use of the drie (deep reactive-ion etching) processing technique. (Machine-translation by Google Translate, not legally binding)
    公开号:ES2610187A1
    申请号:ES201531371
    申请日:2015-09-25
    公开日:2017-04-26
    发明作者:Miguel ULLÁN COMES；Pablo FERNÉNDEZ MARTÍNEZ；Salvador HIDALGO VILLENA；David FLORES GUAL；Enrico GIULIO VILLANI
    申请人:Consejo Superior de Investigaciones Cientificas CSIC；
    IPC主号:
    专利说明:

    JFET TYPE TRANSISTOR AND METHOD OF OBTAINING THE SAME
    D E S C R I P C I ON
    5 OBJECT OF THE INVENTION
    The object of the invention is framed in the field of semiconductor devices and their manufacturing processes.
    10 More specifically, the object of the invention is directed to a JFET type transistor device and a method of obtaining it.
    BACKGROUND OF THE INVENTION
    15 Electronic devices known as JFET (Junction Field-Effect Transistor, in Spanish junction or junction field effect transistor) are circuits based on the electric field effect whose input values are electrical voltages, in particular the voltage between terminals S (source) and G (door), VGS. According to this VGS input value, the JFET transistor output will have a characteristic curve that is simplified by defining three zones with defined equations: cut, ohmic and saturation.
    Physically, a JFET type transistor of the so-called "P-channel" is formed by a P-type semiconductor pickup at the ends of which are located two output terminals 25 (drain and source) flanked by two regions with N-type doping in which connect two terminals connected to each other (door). By applying a positive voltage VGS between door and source, the N zones create around them two areas where the passage of electrons (ID current) is cut off, called exclusion zones. When this VGS exceeds a certain value, the exclusion zones extend to such a point that the passage of ID electrons between source and drain is completely cut off. This value of VGS is called Vp. For a JFET "channel N" the zones p and n are reversed, and the VGS and Vp are negative, the current being cut for voltages lower than Vp (negative).
    Thus, according to the value of VGS, the first two zones are defined; an active one for voltages lower than Vp and a cutting zone for voltages greater than Vp. The different values of the ID depending on the VGS are given by a graph or equation called input equation.
    5
    In the active zone, when the current is allowed, the transistor will output the circuit defined by the drain current (ID) and the voltage between the drain and the VDS source. The graph or equation that relates these two variables is called the output equation, and it is where the two zones of active functioning are distinguished: ohmic and saturation.
    These types of devices are known, along with those procedures for obtaining them; In this sense, several documents are known, such as US8068321B2, which details a conventional JFET for overvoltage protection (protection against unwanted voltage spikes) of a low voltage DC / DC converter. However, the device is a normally off switch that is only activated when it has to protect the main system supporting unwanted current and where the conduction is based on electrons and the technology is based on an initial N + substrate on which grows an N-thin epitaxial layer. Next, implants are performed to create the door (boron) and the source (phosphorus).
    Similarly, document US6251716B1 describes a JFET with low resistance and high switching speed in high current devices (100 A in large area chips). 25 However, the tensile capacity is limited by the thickness of the epitaxial N layer. In addition, the said high switching speed cannot be achieved if a high voltage capacity is required and the conduction is based on electrons and the technology is based on an initial N + substrate, on which a thin N-epitaxial layer is grown, to then create the multiple doors (boron) and the drain region (phosphorus).
    30
    US8310007B2 details a monolithic integration of a lateral NMOS type transistor and a vertical NMOS type transistor, to implement a section of a phase converter. The conduction operation is determined by the configuration of the epitaxial layers N and P grown in the upper part of the N + substrate. The NMOS Gate
    Vertical is created with a trench deeper than that of the upper eitaxial layer type P, finally an N + insulation is included.
    In US6380569B1 a conventional JFET device of high power and high voltage is described, although in normal operation in shutdown and based on conventional N + / N- substrates. In addition, a trench, which includes a gate oxide and the necessary conductive filler material, controls the JFET region. In fact, it has P-type diffusions at the bottom of the trench to prevent premature rupture. The device is aimed at power applications, where the speed of 10 switching is not crucial but where a high current capacity is required.
    Finally, it is that in US20090075435A1 a JFET device is detailed that is based on the use of an insulating region created in the substrate, in an area close to its surface. It is essentially a JFET SOI and as a result, the source, drain and door electrodes have to be placed on the same side of the substrate, resulting in a low voltage and current capacity. The process technologies described in US20090075435A1 are based on the insulating layer and differ from each other in the way the upper semiconductor and doped layer is created. In all cases, a shallow trench is created and filled with polysilicon; The cross section of the JFET proposed in US20090075435A1 is based on electron currents and its topology is such that the JFET proposed in US20090075435A1 provides an extremely fast switching speed and low parasitic level; that is, it is designed for high frequency and low voltage applications.
    25 An electronic device that is widely used by power distribution circuits is the switch. Many of the state-of-the-art switches used in standard application fields are not valid for high radiation applications, since they fail under radiation exposure. In view of the above, one of the concerns of electronic power of today it is the search for appropriate circuits and devices for power distribution in systems that are capable of operating in environments with the presence of radiation, which is harmful.
    5
    10
    fifteen
    twenty
    25
    30
    DESCRIPTION OF THE INVENTION
    In a first aspect of the invention there is a vertical JFET device, that is to say that the current flows from the top of the chip (source) to the bottom (drain), crossing the entire silicon block, while in a second aspect of the invention there is a method for manufacturing the JFET device of the first aspect; method that makes use of the processing technique DRIE (Deep reactive-ion etching). Through the use of the DRIE technique, a series of blind holes are produced that define a trench or more if required, deep in a block of semiconductor material type P, trench that can then be filled with a conductive layer of type A (P or N). These trench is preferably configured with a circular or polygonal section, and defines a body (such as a circular or elliptical section toroid) that encloses a semiconductor volume of type B (N or P) trench; that is to say, seen in plan, the poKgono or circle defined on the surface of the block by the walls of the trench is of a material of type B (N or P) while filling the blind hole / trench with a conductive material of type A (P or N) the trench acts as the gate of the transistor device, while the semiconductor part of the block enclosed between the walls of the trench (the aforementioned circles or poKgonos seen in the plan) will be the intrinsic active part of the JFET transistor, called channel. A source contact and a drain contact are then created. The source contact is created at the top of the surface of the semiconductor block and drain contact is created at the bottom of the semiconductor block so that a JFET transistor deplexion or impoverishment device is obtained, with a vertical configuration.
    The JFET transistor operates as a resistor with the size of the intrinsic conduction volume in those situations in which it is in the linear region near zero or low voltages at the input and low source-drain polarization. In these situations, the source-drain polarization is increased in such a way that there is an increase in voltage in the channel and a voltage drop in the intrinsic conduction volume. The volume of tension in the lower part of the channel is gradually exhausted until it reaches a "throttling" tension in which the volume of tension in the lower part is completely depleted and the current is saturated. On the other hand, if the door tension is increased by inverting the PN junction formed with the intrinsic semiconductor, the volume of channel tension is increasingly impoverished, until it is completely empty in a particular Voff value, and
    as a result there is no current conduction in the channel.
    In an embodiment of the first aspect of the invention, the channel is made of P-type silicon, and the trenches are filled with an N-type material such as polysilicon which can be highly doped. In this way, the device can be used as a radiation resistant power switch in power distribution applications. P-type silicon is not reversed (at type N) because of the damage caused by displacement of non-ionizing radiation, which makes the substrate more resistant to this type of radiation. On the other hand, the only oxides present in the device are on its surface, which makes the device more robust against ionizing radiation damage due to its vertical configuration. Additionally, the radius of the intrinsic channel can be reduced to a low cut-off voltage that allows the use of a low-power control circuit performed with a CMOS sub-micronic CMOS process (DSM), which makes the entire system even more resistant to radiation, since DSM processes are intrinsically more resistant to radiation. In this way, the device can be used as a power switch in energy distribution applications in high radiation environments.
    Among the possible uses of the JFET type transistor of the first aspect of the invention or obtainable by the method of the second aspect of the invention is the use as a switch or as a rad-hard switch (the so-called switch or rad-hard switch).
    DESCRIPTION OF THE DRAWINGS
    25
    To complement the description that is being made and in order to help a better understanding of the characteristics of the invention, according to a preferred example of practical realization thereof, a set of drawings is accompanied as an integral part of said description. where, with an illustrative and non-limiting nature, the following has been represented:
    Figures 1-7.- They show a series of cross-sectional views representative of an alternative embodiment of the process of obtaining the JFET transistor device.
    Figures 8-20.- They show a series of sectional views representative of a preferred embodiment of the process of obtaining the JFET transistor device.
    PREFERRED EMBODIMENT OF THE INVENTION
    5
    In an exemplary embodiment of the invention, the second aspect thereof has to be related to the method of obtaining the JFET transistor device, also referred to throughout this example as a device or simply transistor, from the first aspect of the invention begins In a preferred embodiment of the invention 10 shown in Figures 8 to 20, the second aspect thereof related to the method of obtaining the JFET transistor of the first aspect of the invention is initiated, as observed in Figure 8 with a starting material, a block (1) which is a P-type semiconductor with high resistivity or, alternatively, a P-type semiconductor wafer (1) with very low resistivity on which an epitaxial growth has been performed of a Si layer with high resistivity, grown layer having a thickness of about 100 microns; to subsequently carry out a cleaning (RCA or equivalent), and a growth of a first layer of dielectric (2), such as silicon oxide, by thermal processes to passivate the surface of Si.
    20 A process of making a pattern on the first dielectric layer (2) along with a selective implementation of doping elements (3) of type N is then carried out when the block (1) is of a P-type semiconductor and vice versa with dopants (3) type P when the semiconductor of the block (1) is type N, to subsequently proceed to a thermal process to conform to the result shown in Figure 9. In a possible alternative embodiment it can proceed to grow or deposit a protective layer on those areas that have been doped protective layer that is of a material such as a silicon oxide.
    Next, we proceed to deposit a metal layer that, once defined according to the corresponding pattern, will make a selective mask for the subsequent deep etching of silicon, making a blind hole creating a trench (4), less than 5 microns of width, made in the first dielectric layer (2) and that reaches the inside of the block (1) of semiconductor material, to a depth of about 80 microns, blind hole that is in the form of a crown with a circular section or, alternatively , with
    polygonal section, such that a channel (6) of semiconductor material of the block (1) is defined inside the trench (4). Subsequently, the metal that has been used as a mask is engraved, removing it completely, to obtain a section as in Figure 10. Alternatively, another different material, such as silicon oxide, can be used to mask the deep engraving.
    In a preferred embodiment of the second aspect, the invention, which is the one shown in Figures 8 to 20, the trench (4) made in the block (1) is filled with conductive doped polysilicon (41) whose doping is type P or N as necessary in 10 function of the semiconductor type of the block (1) being doping of the opposite type to the semiconductor of the block (1); also covering part of the surface of the silicon oxide as seen in Figure 11. Subsequently a thermal process is carried out to extend the type dopants from the doped polysilicon to the walls of the trench thus defining a gate (5) of the transistor JFET type of the invention as seen in Figure 12.
    In a possible alternative embodiment of the second aspect of the invention shown in Figures 1 to 7, a doping of the walls of the trench (4) is carried out by thermal diffusion of dopants, and subsequently the trench can be filled with another conductive material different from polysilicon or with an insulating material.
    twenty
    In any of the possible embodiments, a selective etching process of the first dielectric layer (2) is then carried out in a specific area in the center of the channel, to perform a selective implementation of doping elements of type P or N according to if necessary, see previous explanation, only in the areas where the first dielectric layer (2) has been engraved, that is to say silicon oxide, to subsequently proceed to a thermal process to conform to the result shown in Figure 13, defining a source (92) of the transistor.
    Next, a selective implementation process of doping elements 30 of P or N is carried out as necessary on the back of the block (1) to subsequently proceed to a thermal process to form the result shown in Figure 14, defining a drain ( 101) of the transistor.
    Next, a growth or, alternatively, deposit of a second is carried out
    dielectric layer (7) which can be silicon oxide, by thermal processes to function as an insulating layer between conductive layers, as can be seen in Figure 15.
    5 Next, a selective engraving of this second dielectric layer (7) is made in specific areas for the opening of respective contact windows (78,79) to the door (5) and to the source (92) of the transistor as seen in figure 16.
    That is, in those embodiments in which the block (1) is of semiconductor type N, the doping of the conductor (41) that defines the door (5), is of type P and in turn, that of the elements that define the drain (101) and source (92), must be type N and vice versa.
    A first conductive material layer (11) is then deposited on the entire surface as seen in Figure 17, which contacts the door (5) and the source (92) of the transistor. Subsequently, this metal layer is selectively etched in specific areas to electrically define and separate a door contact (81) and a source contact (91) from the transistor as seen in Figure 18.
    In a possible alternative embodiment, the door contact (81) and the source contact 20 (91) are not obtained by separating the first layer of conductive material (11) but are obtained by deposition of a first layer of electrically conductive material of low resistivity (8) that at least partially covers the door (5) and contacts the door (5) defining a door contact (81), and of a second layer of electrically conductive material of low resistivity (9 ) covering at least 25 partially the channel (6) at its top defining the source contact (91).
    Next, a third layer of low-resistive electrical conductive material (10) is deposited that at least partially covers the channel (6) at its bottom on the back of the block (1) as seen in Figure 19, which contacts the drain (101) of the device and defines the drain contact (102) of the device.
    Next, and with the purpose of carrying out a passivation and isolation, a passivation layer (80) is deposited, which comprises a silicon oxide layer of the passivation layer and a silicon nitride layer of the layer of passivation,
    completely covering the contacts (81.91), and the second layer of dielectric (7) there where it is exposed. This passivation layer (80) is subsequently recorded selectively to open contact windows (88.89) to the door contact (81) and to the source contact (91) of the device as seen in Figure 20.
    5
    权利要求:
    Claims (13)
    [1]
    5
    10
    fifteen
    twenty
    25
    30
    RE I V I N D I C A C I O N E S
    1. - JFET type transistor comprising a block (1) of semiconductor material P or N, the JFET type transistor characterized by comprising:
    - a first dielectric layer (2) covering at least partially a surface of the block (1),
    - a trench (4) made in the dielectric layer (2) and that reaches the inside of the block (1) of semiconductor material such that a channel (6) of semiconductor material of the block (1) is defined in the inside the trench (4), where the inner wall of the trench (4) comprises a doped semiconductor material opposite to that of the semiconductor material of the block (1) thereby defining the gate (5) of the JFET transistor,
    - a second dielectric layer (7) covering at least partially the surface of the block (1) and the first dielectric layer (2),
    - a first layer of electrically conductive material of low resistivity (8) that at least partially covers the door (5), and contacts the door (5) defining a door contact (81),
    - a second layer of low-resistive electrical conductor material (9) that at least partially covers the channel (6) at its upper part defining a source contact (91), and
    - a third layer of electrically conductive material of low resistivity (10) that at least partially covers the channel (6) by its lower part defining a drain contact (101).
    [2]
    2. - JFET type transistor according to claim 1 characterized in that the trench (4) having a polygonal or circular crown section.
    [3]
    3. - JFET type transistor according to claim 1 or 2 characterized in that the trench (4) has a depth less than the thickness of the block (1).
    [4]
    4. - JFET type transistor according to any one of embodiments 1 to 3 characterized in that the channel is made of silicon, and the trenches (4) are filled with polysilicon.
    [5]
    5. - JFET type transistor according to claim 1 characterized in that the layer of
    5
    10
    fifteen
    twenty
    25
    30
    Dielectric (7) is made of a material that is selected from silicon dioxide and silicon nitride.
    [6]
    6. - JFET type transistor according to claim 1 characterized in that the trenches (4) have their longitudinal axis orthogonal to the longitudinal plane of the block (1).
    [7]
    7. - JFET type transistor according to claim 1 characterized in that it additionally comprises at least one passivation layer (80) that covers at least partially the dielectric layer (7) and at least one of the layers of low-resistive electrical conductor material ( 8,9,10).
    [8]
    8. - JFET type transistor according to claim 1 characterized in that the passivation layer (80) comprises a silicon oxide layer of the passivation layer and a silicon nitride layer of the passivation layer.
    [9]
    9. - Method of obtaining a JFET transistor, a method characterized by comprising:
    i. grow a first layer of dielectric (2) on a block surface (1),
    ii. stamp the first dielectric layer (2),
    iii. doping at least one area of the block surface (1) through the first dielectric layer (2) with dopants (3) of inverse type to that of the block (1),
    iv. apply a thermal annealing treatment to the result of the previous step,
    v. make a blind hole with a circular or polygonal section crown shape on the first dielectric layer (2), blind hole that reaches an interior area of the block (1) and defines the trench (4),
    saw. deposit a layer of conductive doped polysilicon (41) covering at least partially the dielectric layer (2) and the trench (4) covering the interior of the walls thereof while leaving part of the first dielectric layer (2) exposed,
    vii. Perform a thermal process to extend the N-type dopants from the doped polysilicon to the walls of the trench (4) thus defining the door (5) of the device,
    viii practice at least one selective etching on the first dielectric layer (2)
    defining a window that exposes the surface of the block (1) in the center of the
    12
    5
    10
    fifteen
    twenty
    25
    channel (6), to carry out a selective implementation of doping elements only in areas where silicon oxide has been recorded, to subsequently proceed to a thermal process, defining a source (92),
    ix. Perform a selective implementation process of doping elements on the back of the block (1) and then proceed to a thermal process defining the drain (101) of the device,
    x. depositing a dielectric layer (7) on the doped conductive polysilicon layer (41) doped with a type of semiconductor inverse to that of the block (1), such that it covers said conductive doped polysilicon layer (41) and the rest Of the surface,
    xi. make a selective engraving of this dielectric layer (7) in specific areas for opening contact windows (78,79) to the door (5) and the source (92),
    xii. deposit a first conductive material layer (11), which contacts the door (5) and the source (92) of the transistor,
    xiii. selectively etch the conductive material layer (11) in specific areas to electrically define and separate a door contact (81) and a source contact (91) from the transistor,
    xiv. depositing a third layer of low-resistive electrical conductor material (10) that at least partially covers the channel (6) at its bottom on the back of the block (1), which contacts the drain (101) of the device and defines the contact drain (102) of the device,
    xv. depositing a passivation layer (80) which comprises a silicon oxide layer of the passivation layer and a silicon nitride layer of the passivation layer, completely covering the contacts (81.91), and the second layer of dielectric (7) wherever it is exposed, and
    xvi. engraving the passivation layer (80) selectively to open contact windows (88.89) to the door contact (81) and to the source contact (91).
    [10]
    10. Method according to claim 9 characterized in that the door contact (81) and the source contact (91) are defined by deposition of a first layer of low-resistive electrical conductive material (8) that covers at least partially door (5) and contact the door (5) defining a door contact (81), and a second layer of low-resistive electrical conductor material (9) that covers at least partially the
    channel (6) at the top.
    [11]
    11. - Method according to claim 9 characterized in that it additionally comprises depositing a protective layer of silicon oxide on the area an area of the first
    5 dielectric layer (2) that has been doped in step ii.
    [12]
    12. - Method according to claim 9 characterized in that the trench (4) has a thickness not greater than 5 microns.
    10 13.- Method according to claim 9 characterized in that the trench (4) has a
    depth not greater than 60 to 100 microns.
    [14]
    14. Use of the JFET type transistor described in any one of claims 1 to 8 or obtainable by the method described in any one of claims 9 to 13 as a switch.
    类似技术:
    公开号 | 公开日 | 专利标题
    US10727330B2|2020-07-28|Semiconductor device with diode region
    US20180053841A1|2018-02-22|Semiconductor Device with a Source Trench Electrode
    JP2005510881A|2005-04-21|Trench metal oxide semiconductor field effect transistor device with improved on-resistance
    JP4930904B2|2012-05-16|Electrical circuit switching device
    JP2005510881A5|2006-01-19|
    JP6092749B2|2017-03-08|Semiconductor device and manufacturing method of semiconductor device
    EP2346170A1|2011-07-20|Electric circuit switching device
    JP2018129378A|2018-08-16|Semiconductor device and method of manufacturing the same, and semiconductor wafer structure
    JPWO2015015808A1|2017-03-02|Silicon carbide semiconductor device and manufacturing method thereof
    CN105405867B|2019-07-30|Form the method with the semiconductor substrate of buried chamber and dielectric support structure
    US7186596B2|2007-03-06|Vertical diode formation in SOI application
    TWI566410B|2017-01-11|Semiconductor device, termination structure and method of forming the same
    JP5795452B1|2015-10-14|Silicon carbide semiconductor device, method for manufacturing silicon carbide semiconductor device, and method for designing silicon carbide semiconductor device
    KR101807334B1|2018-01-11|Multi source jfet device
    CA1142271A|1983-03-01|Field effect semiconductor device
    CN109728094A|2019-05-07|FINFET cascade horizontal proliferation semiconductor device
    ES2610187B1|2018-02-07|JFET TYPE TRANSISTOR AND METHOD OF OBTAINING THE SAME
    ES2745740B2|2020-07-30|TRANSISTOR OF BINDING FIELD EFFECT, METHOD OF OBTAINING AND USE OF THE SAME
    JP5638559B2|2014-12-10|Semiconductor device
    KR101964153B1|2019-04-03|Implementation of SiC Semiconductor Devices On SiC Insulation or Semi-insulation Substrate And Manufacturing Methods of The Same
    JP6569216B2|2019-09-04|Insulated gate semiconductor device and manufacturing method thereof
    KR102296258B1|2021-08-30|Trench gate type silicon carbide MOSFET structure and manufacturing method thereof
    JP6809218B2|2021-01-06|Semiconductor devices and methods for manufacturing semiconductor devices
    KR101716957B1|2017-03-15|Junction gate field-effect transistor |, semiconductor device and method of manufacturing
    ES2873116T3|2021-11-03|Monolithically Integrated Hybrid Switch
    同族专利:
    公开号 | 公开日
    ES2610187B1|2018-02-07|
    WO2017051051A1|2017-03-30|
    引用文献:
    公开号 | 申请日 | 公开日 | 申请人 | 专利标题
    US5122851A|1989-04-03|1992-06-16|Grumman Aerospace Corporation|Trench JFET integrated circuit elements|
    US20120313196A1|2009-10-19|2012-12-13|Brookhaven Science Associates ,LLC et al.|3-d trench electrode detectors|ES2745740B2|2018-08-31|2020-07-30|Consejo Superior Investigacion|TRANSISTOR OF BINDING FIELD EFFECT, METHOD OF OBTAINING AND USE OF THE SAME|
    法律状态:
    2018-02-07| FG2A| Definitive protection|Ref document number: 2610187 Country of ref document: ES Kind code of ref document: B1 Effective date: 20180207 |
    2018-07-25| FA2A| Application withdrawn|Effective date: 20180719 |
    优先权:
    申请号 | 申请日 | 专利标题
    ES201531371A|ES2610187B1|2015-09-25|2015-09-25|JFET TYPE TRANSISTOR AND METHOD OF OBTAINING THE SAME|ES201531371A| ES2610187B1|2015-09-25|2015-09-25|JFET TYPE TRANSISTOR AND METHOD OF OBTAINING THE SAME|
    PCT/ES2016/070662| WO2017051051A1|2015-09-25|2016-09-22|Jfet-type transistor and method for the production thereof|
    [返回顶部]